In recent years, the speed of a bus connecting LSIs mounted on a server has reached several GHz. An expensive high-speed bus logic analyzer is required in order to record a transmission/reception history of transactions between LSIs for failure analysis.
FIG. 12 illustrates a configuration utilizing a method of directly probing a high-speed bus, which is one of conventional methods for recording transmission/reception history of transactions of an inter-LSI bus.
An LSI having a high-speed bus interface is an LSI connected to a bus having a transfer frequency of several hundred MHz or more. A high-speed bus is a line of a system board in which a transfer rate of several hundred MHz or more is achieved. A high-speed bus logic analyzer is an observation apparatus specialized for a specific high-speed bus and has a sampling frequency of about several ten GHz. The system board carries LSIs each having a high-speed bus interface on its board substrate. The high-speed bus on the system board and high-speed bus logic analyzer are connected by a probe.
Operation of the conventional inter-LSI bus in the configuration illustrated in FIG. 12 will be described. The high-speed bus for recording a transmission/reception history of transactions and logic analyzer are directly connected by the probe. The transmission/reception history of transactions is recorded in the logic analyzer by an amount corresponding to the capacity of the storage area provided in the logic analyzer.
FIG. 13 illustrates a configuration utilizing a method in which a trace memory for recording a transaction transmission/reception history is provided inside the LSI, which is one of conventional methods for recording transmission/reception history of transactions of the high-speed bus.
The LSI having the high-speed bus interface and high-speed bus are the same as those in FIG. 12. The trace memory for recording a transmission/reception history is a trace memory which is provided inside the LSI and is used for recording transactions transmitted/received through the high-speed bus. When the trace memory is full of the history, the recorded history information is overwritten sequentially from the oldest. The recording of the history is stopped using a transaction event such as exception handling as a trigger. Only while the history recording to the trace memory is in stopped state, the history information recorded in the trace memory is read out into a service processor.
Operation of the transaction transmission/reception history recording method illustrated in FIG. 13 will be described. The trace memory for recording a transmission/reception history is set to a recordable state using an event for starting the transmission/reception history recording as a trigger. During this recordable state, a transaction is transmitted through the high-speed bus to or from the LSI and, at the same time, the transaction is recorded in the trace memory. When the trace memory is full, the recorded information is overwritten sequentially from the oldest. The trace memory is set to a recording stop state using an event that stops the transmission/reception history recording, such as exception handling, as a trigger.
While the trace memory is in recording stopped state, the history information recorded in the trace memory is read out into the service processor. Accordingly, the reception history corresponding to the capacity of the trace memory is recorded.
[Patent Document 1]
Japanese Laid-open Patent Publication No. 2000-293441
However, the above conventional method in which the transaction transmission/reception history is recorded in the high-speed bus logic analyzer has the following problems:
The logic analyzer specialized for the high-speed bus is necessarily expensive because “sampling frequency is high”, “there is a need to perform signal restoration depending on individual protocols in order to increase signal integrity”, or the like.
Since the probe is directly connected to the high-speed bus on the system board, signal integrity is deteriorated due to influence of signal reflection or the like. Thus, an implementation for ensuring the signal integrity is required for the system board.
Further, in the case of the method in which the trace memory for recording a transmission/reception history is provided inside the LSI, the storage size of the trace memory provided inside the LSI as a transmission/reception history storage area becomes very small. In a configuration having one CPU and one DMA transfer device, there is a possibility that a transmission/reception history required for carrying out failure analysis can be collected even if the storage size of the trace memory is small. However, in recent years, a server is often provided with a plurality of CPUs and a plurality of DMA transfer devices, so that there may be a case where a transaction to be checked does not remain in the trace memory.